A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large scale integration has resulted in continued shrinking of device and circuit dimensions and features. In integrated circuits having field-effect transistors, for example, one very important process step is the formation of the gate for each of the transistors, and in particular the dimensions of the gate. In many applications, the performance characteristics (e.g., switching speed) and size of the transistor are functions of the size (e.g., width) of the transistor's gate. Thus, for example, a narrower gate tends to produce a higher performance transistor (e.g., faster) that is inherently smaller in size (e.g., narrower width).
As is often the case, however, there are limitations to existing techniques that reduce their effectiveness or even exclude their use in fabricating the next generation of integrated circuit devices. For example, the limitations of conventional lithographic techniques and tools, which are used to pattern the gates during fabrication, are quickly being realized. Accordingly, there is a continuing need for more efficient and effective fabrication processes for forming transistor gates that are smaller and/or exhibit higher performance.